Digital-to-Analog Converters (DACs) are decoding devices (electrical circuits) that convert digital data to its corresponding analog signal. One of the challenges associated with DAC performance is that it may be difficult to achieve an ideal output voltage. There are various static and dynamic measures of DAC performance. Static measures include Differential Non-Linearity (DNL) error, Integral Non-Linearity (INL) error, Monotonicity, Offset Error, Gain Error. Dynamic measures include Glitch, Settling Time, Signal-to-Noise Ratio (SNR), Spurious-Free Dynamic Range (SFDR), and the like.
In many applications, the use of DACs is straightforward. However, in some other applications, high-resolution DACs are used for calibration purposes. For example, Calibration DACs (CDACs) can be used to control the gain of a circuit that includes Op amps and 8 resistors; an 8-bit calibration DAC was used to make gain and offset adjustments in a pressure sensor, etc.
There are various types of DAC topologies, such as Thermometer-coded DAC, binary weighted DACs, Pulse Width Modulated (PWM) DACs, Pulse Density Modulated (PDM) DAC, hybrid DACs, current steering and stitched resistor DACs. Each of these architectures has their own pros and cons in terms of resolution, area occupancy, power consumption, monotonicity and settling times. Thermometer-coded DACs use 2N-1 equal size number of elements (current sources, resistors or capacitors). For instance, designing an 8-bit current mode DAC using this architecture would require using 255 current sources of equal quantity. This is the reason the digital input must be in the form of a thermometer code, and a thermometer decoder is needed to convert binary inputs into thermometer codes. The main advantage of this architecture is guaranteed monotonicity. However, area occupancy and power consumption are high. That is the reason they are rarely used for high-resolution DACs.
Binary weighted DACs utilize a binary weighted number of elements. For example, designing an 8-bit current-mode DAC using this architecture would require using 8 current sources only, which makes it area efficient compared to its thermometer-coded counterpart. One of the drawbacks of this architecture is that for high-resolution designs (>10 bits), the difference between the Most Significant Bits (MSBs) and Least Significant Bits (LSBs) weights is large and the output becomes very sensitive to mismatch errors and glitches. This might lead to a non-monotonic DAC. In addition, the number of elements (current sources) that needs calibration is still high.
Hybrid DACs use a combination of the architectures indicated above. The most common type of hybrid DACs is the segmented (Two-Path) DAC. In this DAC, the thermometer-coded architecture is used for the MSBs, and the binary weighted one is used for the LSBs. This makes use of the advantages offered by the two architectures. Segmented DACs are often used to design high resolution and low area/power devices. However, it is always a challenge to find the optimum number of segmentations, i.e., the number of bits that should be thermometer-coded. In addition, the need of the complex circuitry for the thermometer-coded architecture is not totally resolved in segmented DACs. For high-resolution DACs, Dynamic Element Matching (DEM) is widely used to compensate for matching errors that affect the linearity of the DAC. This technique is implemented using encoders which are complex and burn a lot of energy.
Known systems and methods of designing gain control loops have utilized a single DAC to convert the processed digital gain to an analog signal controlling the gain of the amplifier. Such systems achieve results having very stringent DAC specifications, e.g., equivalent number of bits (ENOB), DNL, INL, power, and size. Such systems require an ENOB of 16-bits with very tight DNL/INL specs (less than 1<LSB). This results in very large, power-hungry DACs that need oversampling, i.e. Sigma-Delta (ΣΔ).